This invention relates to the field of semiconductor manufacturing, and more particularly to a method used in the fabrication of a semiconductor device to provide a conductive plug or other feature. In-process structures resulting from the inventive method are also described.
During the manufacture of a semiconductor device such as a dynamic random access memory (DRAM), static RAM (SRAM), and other memories, microprocessors, and logic devices, several structures are commonly formed. For example, contact openings in one or more dielectric layers are typically used to expose an underlying layer such as a conductive land. A conductive layer is then formed within the opening to contact the land and to provide electrical access to the pad. Trenches are also formed, for example to define conductive interconnects.
FIGS. 1 and 2 depict a process to form openings to conductive lands. FIG. 1 depicts a wafer substrate assembly 10 comprising a semiconductor wafer 12 with conductive lands 14, a first dielectric layer 16 between about 2,000 angstroms (xc3x85) and about 2,600 xc3x85 thick, for example about 2,300 xc3x85 thick, and a second dielectric layer 18 between about 3,000 xc3x85 thick and about 3,600 xc3x85 thick, for example about 3,300 xc3x85 thick. FIG. 1 further depicts conductive polysilicon pads 20 which are electrically coupled with lands 14. Also depicted in FIG. 1 is a first borophosphosilicate glass (BPSG) layer 22 between about 15,000 xc3x85 and about 15,600 xc3x85 thick, preferably about 15,300 xc3x85 thick. Further depicted is a second BPSG layer 23 between about 2,700 xc3x85 and about 3,300 xc3x85 thick, for example about 3,000 xc3x85 thick, and portions of a polysilicon capacitor top plate 24 between about 500 xc3x85 and about 700 xc3x85 thick, for example about 600 xc3x85 thick. The capacitor top plate comprising portions 24 is formed after forming BPSG 22, and prior to forming BPSG 23.
Next, a patterned photoresist layer 26 is formed which defines openings 28 which overlie the conductive pads 20. Other structures may also be formed which are not depicted depending on the type of device, such as storage capacitors for use with a dynamic random access memory (DRAM) device. FIG. 1 is generally to scale, except the photoresist will be between about 6,000 xc3x85 and 8,000 xc3x85 thick for this exemplary structure. The spacing between each photoresist feature 26 is about 2,700 xc3x85 and the pitch is about 6,700 xc3x85.
After forming the structure of FIG. 1, a vertical anisotropic oxide dry etch is performed to remove the exposed BPSG 22, 23 in an attempt to result in the structure of FIG. 2. A portion of the photoresist, typically about 90% is removed during the etch.
Various problems can occur during the etch of the BPSG 23, 24 of FIG. 1. For example, while etching the openings there is a tendency for a positive charge to build up at the bottom of the openings while a negative charge is generated at the top. As a result, positively charged ions which are used to etch the openings have difficulty reaching the bottom of the opening where they are needed to continue etching the openings to expose the conductive lands 20. This can result in a slowing or cessation of the etch before the material is completely removed from the lands or other features, and can also result in profile anomalies.
A method which reduces or eliminates the problems described above would be desirable.
The present invention provides a new method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from electrical charges building up along an opening during a dielectric or other etch. In accordance with one embodiment of the invention an etch is performed in a dielectric layer as deep as possible before the charge buildup unduly interferes with the etching process. Then, conductive spacers are provided in the opening, for example by forming a chemical vapor deposited (CVD) metal layer into the openings, followed by a spacer etch. The spacers provide a conductive path between the negatively-charged top and the positively-charged bottom. Optionally, etching may then continue with the conductive spacers in place to assist in the charge recombination between the top and bottom of the feature. These steps may also be repeated two or more times until the desired trench depth is reached.
In an alternate embodiment, a gas additive is used during the etch process which will adsorb on the sidewalls of the etched features and allow improved electrical conduction along the sidewalls. The gas may run at a continuous flow during the process, pulsed, or run as a separate etch step, and various gasses may be used as detailed below.
Additional advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.